ABOUT
iPronics aims to expand photonics processing to all the layers of the industry. This game-changing technology has a wide range of applications, including 5/6 G communications, intelligent transceivers and switches, tensor cores for neuromorphic computing, lidar and aerospace surveillance and communications
The total non-recoverable engineering costs for developing a single iteration of an application specific photonic integrated circuit (ASPIC) design are around €550k-€1,700k, and the development time is currently 12 months. As the original ASPIC design is rarely error-free, typically 2-3 iterations are required, taking the cumulative effort to 2-3 years and the cost into the region of €940k-€4.6m.
iPronics cuts the typical development time of an ASPIC by 90% and the associated costs by 95%. A new design is simply reprogrammed, downloaded into the chip and tested in a matter of hours, eliminating the need for expensive and time-consuming manufacturing runs.
Competitive advantage of programmable technology
See our current innovative projects
INSPIRE
- EIC Transition Open under the grant agreement 101057934.
- Our project INSPIRE will make programmable photonic processor available in form of TRL5/6 demonstrators for the first time. This project will advance our current technology readiness by increasing the number of programmable unit cells per chip and improving key performance characteristics including power consumption, space requirements and chip coupling losses. This new optical layer design is then produced in a pilot batch ready for functional tests, validation and demonstration.
- More information in CORDIS website
PROMETHEUS
- Horizon Europe Digital Emerging
- This project aims at leveraging programmable photonics to develop neuromorphic architectures, such as largescale photonic spiking neural networks, exploiting multiplexing and the GHz firing rate of integrated laser-neurons, convolutional networks for edge detection, on-chip training and the disruptive exploration of quantum reservoir computing schemes. The platform will put into practice also as an integrated quantum random generator and as a physical unclonable function, adding authentication and physical layer encryption to the chip.
AWARDS
SUPPORTED BY
“DOCTORADOS INDUSTRIALES” DIN2019-010891
