About

iPronics aims to expand photonics processing to all the layers of the industry. This game-changing technology has a wide range of applications, including 5/6 G communications, intelligent transceivers and switches, tensor cores for neuromorphic computing, lidar and aerospace surveillance and communications

The total non-recoverable engineering costs for developing a single iteration of an application specific photonic integrated circuit (ASPIC) design are around €550k-€1,700k, and the development time is currently 12 months. As the original ASPIC design is rarely error-free, typically 2-3 iterations are required, taking the cumulative effort to 2-3 years and the cost into the region of €940k-€4.6m.

iPronics cuts the typical development time of an ASPIC by 90% and the associated costs by 95%. A new design is simply reprogrammed, downloaded into the chip and tested in a matter of hours, eliminating the need for expensive and time-consuming manufacturing runs.

Competitive advantage of programmable technology

See our current innovative projects

INSPIRE

EIC Transition Open under the grant agreement 101057934.
Our project INSPIRE will make programmable photonic processor available in form of TRL5/6 demonstrators for the first time. This project will advance our current technology readiness by increasing the number of programmable unit cells per chip and improving key performance characteristics including power consumption, space requirements and chip coupling losses. This new optical layer design is then produced in a pilot batch ready for functional tests, validation and demonstration.
More information in CORDIS website

PROMETHEUS

Horizon Europe Digital Emerging
This project aims at leveraging programmable photonics to develop neuromorphic architectures, such as largescale photonic spiking neural networks, exploiting multiplexing and the GHz firing rate of integrated laser-neurons, convolutional networks for edge detection, on-chip training and the disruptive exploration of quantum reservoir computing schemes. The platform will put into practice also as an integrated quantum random generator and as a physical unclonable function, adding authentication and physical layer encryption to the chip.
More information in CORDIS website

ALLEGRO

ALLEGRO will develop an autonomous and HW sliceable optical network that not only enables secure and energy-efficient services, but it also adds new capabilities such as:

Ultra-low latency and low-energy switching solutions to support edge computing by deploying:
- Smart, coherent transceivers exploiting multi-band & multi-fiber technologies for P2P and P2MP applications, based on e.g., high-speed plasmonic modulators/photodetectors and programmable silicon photonic integrated waveguide meshes.
- Loss-less, energy-efficient transparent photonic integrated optical switches, eliminating OEO conversions, e.g., with on-chip amplification in the O-band for datacom applications.
Intensive virtualization and a high degree of softwarization to enable flexible and dynamic HW configuration.
A monitoring, sensing and telemetry plane to alert at both the network infrastructure level as well as at the geographical footprint level.
A convergence between metro and access domain to reduce cost and power consumption, also by removing unneeded elements in the network as for example employing P2MP pluggables.
Enhanced optical data plance security by introducing quantum key distribution (QKD) with improved protocol security and better performance, post-quantum cryptography (PQC).
A deterministic time synchronization mechanism layer for ultra-low latency applications implemented by a HW programmable physical layer.

iPronics Programmable Photonics will provide a reconfigurable and smart photonic interconnect to develop the smart coherent transceiver including data processing in the optical domain (dispersion compensation, noise removal, correction of the polarization fluctuations and equalization of the coherent detection) and an on-chip fibre interrogator, all functions controlled by Software.

Additionally, the same chips will be used to provide a switch operating in the C-band.

More information in Project page Allegro and Project page (EU)

AWARDS

SUPPORTED BY

AYUDAS PARA LA FORMACIÓN DE DOCTORES EN EMPRESAS
“DOCTORADOS INDUSTRIALES” DIN2019-010891